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RTL8110SC-GR rtl8110scl-gr integrated gigabit ethernet controller (lom) (minipci) datasheet rev. 1.3 09 january 2007 track id: jatr-1076-21 realtek semiconductor corp. no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com.tw www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) ii track id: jatr-1076-21 rev. 1.3 copyright ?2007 realtek semiconductor corp. all rights reserve d. no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of realtek semiconductor corp. trademarks realtek is a trademark of realtek semiconductor cor poration. other names mentioned in this document are trademarks/registered trademarks of their respective owners. disclaimer realtek provides this document ?as is?, without wa rranty of any kind, neither expressed nor implied, including, but not limited t o, the particular purpose. realtek may make improvements and/or changes in this document or in the product described in this document at any time. this document could include technical inaccuracies or typographical errors. using this document this document is intended for use by the softwa re engineer when pr ogramming for realtek rtl8110sc(l) controller chips. information pertaini ng to the hardware design of products using these chips is contained in a separate document. though every effort has been made to ensure that th is document is current and accurate, more information may have become available subsequent to the producti on of this guide. in that event, please contact your realtek representative for additional information that may help in the development process. revision history revision release date summary 1.0 2005/08/11 first release. 1.1 2005/09/14 added all model numbers to front page. 1.2 2005/11/14 corrected e values on page 35. revised section 9 ordering information, page 38. 1.3 2007/01/09 pin 116 (vdd15) changed to not connected. pin 118 (gnd) changed to not connected. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) iii track id: jatr-1076-21 rev. 1.3 table of contents 1. general description............................................................................................................ ....................................1 2. features....................................................................................................................... ....................................................2 3. system applications ............................................................................................................ .....................................2 4. pin assignments ................................................................................................................ ...........................................3 4.1. p ackage i dentification ............................................................................................................................... ............3 5. pin descriptions ............................................................................................................... ...........................................4 5.1. p ower m anagement /i solation ............................................................................................................................... 4 5.2. pci i nterface ............................................................................................................................... .............................5 5.3. eeprom ......................................................................................................................... ...........................................7 5.4. t ransceiver i nterface ............................................................................................................................... .............7 5.5. c lock ............................................................................................................................... ..........................................7 5.6. r egulator & r eference ............................................................................................................................... ...........7 5.7. led s ............................................................................................................................... ............................................8 5.8. p ower & g round ............................................................................................................................... .......................8 5.9. nc (n ot c onnected ) p ins ............................................................................................................................... .........8 6. functional description......................................................................................................... ................................9 6.1. pci b us i nterface ............................................................................................................................... ......................9 6.1.1. byte or dering .................................................................................................................. .......................................9 6.1.2. interrupt control .............................................................................................................. ......................................9 6.1.3. latency timer .................................................................................................................. .....................................10 6.1.4. 64-bit addr essing .............................................................................................................. ...................................10 6.2. pci b us o peration ............................................................................................................................... ...................10 6.2.1. target read.................................................................................................................... .......................................10 6.2.2. target write ................................................................................................................... ....................................... 11 6.2.3. master read .................................................................................................................... .....................................12 6.2.4. master write ................................................................................................................... ......................................13 6.2.5. configuratio n acces s........................................................................................................... .................................13 6.3. led f unctions ............................................................................................................................... .........................14 6.3.1. link monitor................................................................................................................... ......................................14 6.3.2. rx led ......................................................................................................................... ........................................14 6.3.3. tx led ......................................................................................................................... ........................................15 6.3.4. tx/rx led ...................................................................................................................... ......................................16 6.3.5. link/act led ................................................................................................................... .................................17 6.4. phy t ransceiver ............................................................................................................................... .....................18 6.4.1. phy tran smitter ................................................................................................................ ...................................18 6.4.2. phy r eceiver................................................................................................................... .....................................18 6.5. n ext p age ............................................................................................................................... .................................18 6.6. eeprom i nterface ............................................................................................................................... .................19 6.7. p ower m anagement ............................................................................................................................... ................19 7. characteristics ................................................................................................................ .......................................22 7.1. a bsolute m aximum r at i n g s ............................................................................................................................... ..22 7.2. r ecommended o perating c onditions .................................................................................................................22 7.3. c rystal r equirements ............................................................................................................................... ...........22 7.4. t hermal c haracteristics ............................................................................................................................... ......23 7.5. dc c haracteristics ............................................................................................................................... ................23 7.6. ac c haracteristics ............................................................................................................................... ................24 7.6.1. serial eeprom in terface timing ................................................................................................. .......................24 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) iv track id: jatr-1076-21 rev. 1.3 7.7. pci b us o peration t iming ............................................................................................................................... ......25 7.7.1. pci bus timing parameters ...................................................................................................... ...........................25 7.7.2. pci clock sp ecifica tion ........................................................................................................ ...............................26 7.7.3. pci transactions ............................................................................................................... ...................................27 8. mechanical dimensions .......................................................................................................... .............................34 8.1. 128-p in qfp m echanical d imensions ..................................................................................................................34 8.2. n otes for 128-p in qfp d imensions ......................................................................................................................35 8.3. 128-p in lqfp m echanical d imensions ................................................................................................................36 8.4. n otes for 128-p in lqfp d imensions ....................................................................................................................37 9. ordering information........................................................................................................... ...............................38 list of tables t able 1. p ower m anagement /i solation ............................................................................................................................... 4 t able 2. pci i nterface ............................................................................................................................... ..............................5 t able 3. eeprom ......................................................................................................................... ............................................7 t able 4. t ransceiver i nterface ............................................................................................................................... .............7 t able 5. c lock ............................................................................................................................... ...........................................7 t able 6. r egulator & r eference ............................................................................................................................... ...........7 t able 7. led s ............................................................................................................................... .............................................8 t able 8. p ower & g round ............................................................................................................................... ........................8 t able 9. nc (n ot c onnected ) p ins ............................................................................................................................... ..........8 t able 10. eeprom i nterface ............................................................................................................................... .................19 t able 11. a bsolute m aximum r atings ............................................................................................................................... .22 t able 12. r ecommended o perating c onditions .................................................................................................................22 t able 13. c rystal r equirements ............................................................................................................................... ...........22 t able 14. t hermal c haracteristics ............................................................................................................................... ......23 t able 15. dc c haracteristics ............................................................................................................................... ................23 t able 16. eeprom a ccess t iming p arameters ..................................................................................................................24 t able 17. pci b us t iming p arameters ............................................................................................................................... ...25 t able 18. m easurement c ondition p arameters .................................................................................................................26 t able 19. c lock and r eset s pecifications ..........................................................................................................................27 t able 20. o rdering i nformation ............................................................................................................................... ...........38 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) v track id: jatr-1076-21 rev. 1.3 list of figures f igure 1. 128-p in (l)qfp p in a ssignments ............................................................................................................................3 f igure 2. l ittle -e ndian b yte o rdering ............................................................................................................................... .9 f igure 3. b ig -e ndian b yte o rdering ............................................................................................................................... ......9 f igure 4. t arget r ead o peration ............................................................................................................................... .........10 f igure 5. t arget w rite o peration ............................................................................................................................... .......11 f igure 6. m aster r ead o peration ............................................................................................................................... ........12 f igure 7. m aster w rite o peration ............................................................................................................................... .......13 f igure 8. r x led............................................................................................................................ .........................................14 f igure 9. t x led............................................................................................................................ .........................................15 f igure 10. t x /r x led ............................................................................................................................ ..................................16 f igure 11. link/act led ............................................................................................................................ ..........................17 f igure 12. s erial eeprom i nterface t iming ......................................................................................................................24 f igure 13. o utput t iming m easurement c onditions .........................................................................................................25 f igure 14. i nput t iming m easurement c onditions .............................................................................................................26 f igure 15. 3.3v c lock w aveform ............................................................................................................................... ..........26 f igure 16. c lock s kew d iagram ............................................................................................................................... ............27 f igure 17. i/o r ead ............................................................................................................................... ...................................27 f igure 18. i/o w rite ............................................................................................................................... ..................................28 f igure 19. c onfiguration r ead ............................................................................................................................... ..............28 f igure 20. c onfiguration w rite ............................................................................................................................... ............29 f igure 21. b us a rbitration ............................................................................................................................... .....................29 f igure 22. m emory r ead b elow 4gb............................................................................................................................ ........30 f igure 23. m emory w rite b elow 4gb............................................................................................................................ ......30 f igure 24. t arget i nitiated t ermination - d isconnect .....................................................................................................31 f igure 25. t arget i nitiated t ermination - a bort ..............................................................................................................31 f igure 26. m aster i nitiated t ermination - a bort .............................................................................................................32 f igure 27. p arity o peration ? o ne e xample .......................................................................................................................32 f igure 28. m emory r ead a bove 4gb (dac) ........................................................................................................................33 f igure 29. m emory w rite a bove 4gb (dac) ......................................................................................................................33 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 1 track id: jatr-1076-21 rev. 1.3 1. general description the realtek rtl8110sc(l) lom gigabit ethernet controller combines a triple-speed ieee 802.3 compliant media access controller (mac) with a tr iple-speed ethernet transceiver, 32-bit pci bus controller, and embedded memory. with state- of-the-art dsp technology and mixed-mode signal technology, it offers high-speed transmission over ca t 5 utp or cat 3 utp (10mbps only) cable. functions such as crossover detection & auto-co rrection, polarity correcti on, adaptive equalization, cross-talk cancellation, echo can cellation, timing recovery, and erro r correction are implemented to provide robust transmission and rece ption capability at high speeds. the device supports the pci v2.2 and minipci v1.0 bus interfaces for host communications with power management, and is compliant with the ieee 802.3 sp ecification for 10/100mbps ethernet and the ieee 802.3ab specification for 1000mbps ethernet. it also s upports an auxiliary power auto-detect function, and will auto-configure related bits of the pci power management regi sters in pci configuration space. to achieve the most efficient power management po ssible, advanced configur ation and power interface (acpi) power management support is provided fo r modern operating systems that are capable of operating system directed power management (ospm ). pci message signaled interrupt (msi) is also supported. in addition to the acpi feature, the rtl8110sc( l) supports remote wake-up (including amd magic packet, re-linkok, and microsoft ? wake-up frame) in both acpi and apm (advanced power management) environments. the lwake pin provides four different output si gnals including active high, active low, positive pulse, and negative pulse . the versatility of the lwake pin provides motherboards with wake-on-lan (w ol) functionality. to support wol from a deep power down state (e.g. d3cold, i.e. main power is off and only auxiliary exists), the auxiliary power source must be able to provide the needed power for the rtl8110sc(l). the rtl8110sc(l) is fully compliant with microsoft ? ndis5 (ip, tcp, udp) checksum and segmentation task-offload features, and supports ieee 802 ip layer 2 priority encoding and 802.1q virtual bridged local area network (vlan). the above features contribute to lowering cpu utilization, especially benefiting performance when in operati on on a network server. also, the devices boost their pci performance by supporting pci memory read li ne & memory read multiple when transmitting, and memory write and invalidate when receiving. to better qualify for server use, the rtl8110sc(l) support the pci dual address cycle (dac) command when the assigned buffers reside at a physical memory address higher than 4 gigabytes. see section 9, ordering information, page 38 for package type details. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 2 track id: jatr-1076-21 rev. 1.3 2. features ? integrated 10/100/1000 transceiver ? auto-negotiation with next page capability ? supports pci rev.2.3, 32-bit, 33/66mhz ? supports clkrunb and minipci v1.0 ? supports pair swap/polarity/skew correction ? crossover detection & auto-correction ? wake-on-lan and remote wake-up support ? microsoft ? ndis5 checksum offload (ip, tcp, udp) and largesend offload support ? supports full duplex flow control (ieee 802.3x) ? fully compliant with ieee 802.3, ieee 802.3u, ieee 802.3ab ? supports ieee 802.1p layer 2 priority encoding ? supports ieee 802.1q vlan tagging ? serial eeprom ? 3.3v signaling, 5v pci i/o tolerant ? transmit/receive fifo support ? supports power down/link down power saving ? supports pci message signaled interrupt (msi) ? various 128-pin package types available 3. system applications ? gigabit ethernet on motherboard ? gigabit ethernet minipci card www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 3 track id: jatr-1076-21 rev. 1.3 4. pin assignments figure 1. 128-pin (l)qfp pin assignments 4.1. package identification green package is indicated by a ?g? in the location marked ?t? in figure 1. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 4 track id: jatr-1076-21 rev. 1.3 5. pin descriptions the following signal type code s are used in the tables: i: input. o: output. t/s: tri-state bi-direc tional input/output pin. s/t/s: sustained tri-state. o/d: open drain. 5.1. power management/isolation table 1. power management/isolation symbol type pin no description pmeb (pme#) o/d 31 power management event: open drain, active low. used to request a change in the current power management state and/or to indicate that a power management event has occurred. isolateb (isolate#) i 23 isolate pin: active low. used to isolate the rtl8110sc(l) from the pci bus. the rtl8110sc(l) will not drive its pci outputs (excluding pme#) and will not sample its pci input (including pcirstb and pciclk) as l ong as the isolate pin is asserted. lanwake o 105 lan wake-up signal (when cardb_en=0, bit2 config3): this signal is used to inform the mother board to execute the wake-up process. the motherboard must support wake-on-lan (wol). there are 4 choices of output that may be asserted from the lanwake pin (active high, active low, positive pulse, and negative pulse). we can co nfigure the lanwake output via two config bits: lwact (config1.4) and lwptn (config4.2). lwact lwake output 0 1 0 active high active low lwptn 1 positive pulse negative pulse the default output is an active high si gnal. once a pme event is received, the lanwake and pmeb assert at the same time when the lwpme (bit4, config4) is set to 0. if the lwpme is set to 1, the lanwake asserts only when pmeb asserts and isolateb is low. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 5 track id: jatr-1076-21 rev. 1.3 5.2. pci interface table 2. pci interface symbol type pin no description pciadpin31-0 t/s 33, 34, 36, 37, 39, 40, 42, 43, 47, 49, 50, 53, 55, 57, 58, 59, 79, 82, 83, 85, 86, 87, 89, 90, 93, 95, 96, 97, 98, 102, 103, 104 ad31-0: low 32-bit pci address and data multiplexed pins. the address phase is the first clock cycle in which frameb is asserted. during the address phase, ad31-0 contai ns a physical address (32 bits). for i/o, this is a byte address, and for configuration and memory, it is a double-word address. the rtl8110sc(l) supports both big-endian and little-endian byte ordering. write data is stable and valid when irdyb is asserted. read data is stable and valid when trdyb is asserted. data i is transferred during those clocks where both irdyb and trdyb are asserted. cbebpin7-4 t/s pci bus command and byte enables multiplex pins. during the address phase of a transaction, cbebpin7-4 defines the bus command. during the data phase, cbebpin7-4 are used as byte enables. the byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. cbebpin4 applies to byte 4, and cbebpin7 applies to byte 7. cbebpin3-0 t/s 44, 60, 77, 92 pci bus command and byte enables multiplex pins. during the address phase of a transaction, cbebpin3-0 defines the bus command. during the data phase, cbebpin3-0 are used as byte enables. the byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. cbebpin0 applies to byte 0, and cbebpin3 applies to byte 3. pciclk i 28 pci clock: this clock input provides timing for all pci transactions and is input to the pci device. support s up to a 66mhz pci clock. clkrunb i/o 65 clock run: this signal is used by the rtl8110sc(l) to request starting (or speeding up) of the pciclk clock. clkrunb also indicates the clock status. for the rtl8110sc(l), clkrunb is an open drain output as well as an input. the rtl8110sc(l) requests the central resource to start, speed up, or maintain the interface clock by the assertion of clkrunb. for the host system, it is an s/t/s signal. the host system (central resource) is responsible for maintaining clkrunb asserted, and for driving it high to the negated (deasserted) state. devselb s/t/s 68 device select: as a bus master, the rtl8110sc(l) samples this signal to insure that a pci target recognizes the destination address for the data transfer. as a target, the rtl8110sc(l) asserts this signal low when it recognizes its target address after frameb is asserted. frameb s/t/s 61 cycle frame: as a bus master, this pin indicates the beginning and duration of an access. frameb is asserted low to indicate the start of a bus transaction. while frameb is assert ed, data transfer continues. when frameb is de-asserted, the transaction is in the final data phase. as a target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it. gntb i 29 grant: this signal is asserted low to indicate to the rtl8110sc(l) that the central arbiter has granted the ownership of the bus to the rtl8110sc(l). this input is used when the device is acting as a bus master. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 6 track id: jatr-1076-21 rev. 1.3 symbol type pin no description reqb t/s 30 request: the rtl8110sc(l) will assert this signal low to request the ownership of the bus from the central arbiter. idsel i 46 initialization device select: this pin allows the device to identify when configuration read/write tran sactions are intended for it. intab o/d 25 interrupt a: used to request an inte rrupt. it is asserted low when an interrupt condition occurs, as defined by the interrupt status, interrupt mask. irdyb s/t/s 63 initiator ready: this indicates the initiating agent?s ability to complete the current data phase of the transaction. as a bus master, this signal will be a sserted low when the device is ready to complete the current data phase transaction. this signal is used in conjunction with the trdyb signal. da ta transaction takes place at the rising edge of clk when both irdy b and trdyb are asserted low. as a target, this signal indicates that the master has put data on the bus. trdyb s/t/s 67 target ready: this indicates the target agent?s ability to complete the current phase of the transaction. as a bus master, this signal indicates that the target is ready for the data during write operations, or is read y to provide the data during read operations. as a target, this signal will be asserted low when the (slave) device is ready to complete the current data phase transaction. this signal is used in conjunction with the irdyb signal. da ta transaction takes place at the rising edge of clk, when both ir dyb and trdyb are asserted low. par t/s 76 parity: this signal indicates even parity across pciadpin31-0 and cbeb3-0 including the par pin. par is stable and valid one clock after each address phase. for data phase, par is stable and valid one clock after either irdyb is asserted on a write tr ansaction or trdyb is asserted on a read transaction. once par is valid, it remains valid until one clock after the completion of the current data phas e. as a bus master, par is asserted during address and write data phases. as a target, par is asserted during read data phases. m66en i 88 66mhz_enable: this pin indicates to the device whether the bus segment is operating at 66 or 33mhz. when this pin (active high) is asserted, the current pci bus segment th at the device resides on operates in 66mhz mode. if this pin is de-asserted, the current pci bus segment operates in 33mhz mode. perrb s/t/s 70 parity error: this pin is used to re port data parity errors during all pci transactions except a special cycle. perrb is driven active (low) two clocks after a data parity error is de tected by the device receiving data, and the minimum duration of perrb is one clock for each data phase with parity error detected. serrb o/d 75 system error: if an address parity erro r is detected and configuration space status register bit 15 (detect parity er ror) is enabled, the device asserts the serrb pin low and bit 14 of the status register in configuration space. stopb s/t/s 69 stop: indicates that the current target is requesting the master to stop the current transaction. pcirstb i 27 reset: when pcirstb is asserted low, the device performs an internal system hardware reset. pcirstb must be held for a minimum period of 120ns. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 7 track id: jatr-1076-21 rev. 1.3 5.3. eeprom table 3. eeprom symbol type pin no description eesk o 111 serial data clock. eedi/aux o/i 109 eedi: output to serial data input pin of eeprom. aux: input pin to detect if aux. powe r exists or not on initial power-on. this pin should be connected to eeprom. to support wakeup from acpi d3cold or apm power-down, this pin must be pulled high to aux. power via a resistor. if this pin is not pulled high to aux. power, the rtl8110sc(l) assumes that no aux. power exists. eedo i 108 input from serial data output pin of eeprom. eecs o 106 eecs: eeprom chip select. 5.4. transceiver interface table 4. transceiver interface symbol type pin no description mdi[0]+ i/o 1 mdi[0] ? i/o 2 in mdi mode, this is the first pair in 1000base-t, i.e. the bi_da+/- pair, and is the transmit pair in 10base-t and 100base-tx. in mdi crossover mode, this pair acts as the bi_db+/- pair, and is the receive pair in 10base-t and 100base-tx. mdi[1]+ i/o 5 mdi[1] ? i/o 6 in mdi mode, this is the second pair in 1000base-t, i.e. the bi_db+/- pair, and is the transmit pair in 10base-t and 100base-tx. in mdi crossover mode, this pair acts as the bi_da+/- pair, and is the transmit pair in 10base-t and 100base-tx. mdi[2]+ i/o 14 mdi[2] ? i/o 15 in mdi mode, this is the third pair in 1000base-t, i.e. the bi_dc+/- pair. in mdi crossover mode, this pair acts as the bi_dd+/- pair. mdi[3]+ i/o 18 mdi[3] ? i/o 19 in mdi mode, this is the fourth pair in 1000base-t, i.e. the bi_dd+/- pair. in mdi crossover mode, this pa ir acts as the bi_dc+/- pair. 5.5. clock table 5. clock symbol type pin no description xtal1 i 121 input of 25mhz clock reference. xtal2 o 122 output of 25mhz clock reference. 5.6. regulator & reference table 6. regulator & reference symbol type pin no description ctrl18 o 8 regulator control. voltage control to external 1.8v regulator. ctrl15 o 125 regulator control. voltage control to external 1.5v regulator. rset i 127 reference. external resistor reference. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 8 track id: jatr-1076-21 rev. 1.3 5.7. leds table 7. leds symbol type pin no description led0 o 117 led1 o 115 led2 o 114 led3 o 113 leds1-0 00 01 10 11 led0 tx/rx act(tx/rx) tx link10/ act led1 link100 link10/100/ 1000 link10/100 /1000 link100/ act led2 link10 full rx full led3 link1000 - full link1000/ act note 1: during power down mode , the led signals are logic high. note 2: leds1-0?s initial valu e comes from 93c46/93c56/93c66. 5.8. power & ground table 8. power & ground symbol type pin no description avdd15 power 126 analog 1.5v power supply. vdd15 power 24, 32, 45, 54, 64, 78, 99, 110 digital 1.5v power supply. vdd33 power 26, 41, 56, 71, 84, 94, 107 digital 3.3v power supply. gnd/vsspst power 21, 22, 35, 38, 48, 51, 52, 62, 66, 73, 80, 81, 91, 100, 101, 112, 119 digital ground. avdd18 power 3, 7, 16, 20 analog 1.8v power supply. avdd33 power 10, 12, 120 analog 3.3v power supply. vss power 4, 9, 11, 13, 17, 123, 124, 128 analog ground. 5.9. nc (not connected) pins table 9. nc (not connected) pins symbol type pin no description nc 72, 74, 116, 118 not connected. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 9 track id: jatr-1076-21 rev. 1.3 6. functional description 6.1. pci bus interface the rtl8110sc(l) implements the pc i bus interface as defined in the pci local bus specifications rev. 2.3. when internal registers are being accessed, the rtl8110sc(l) acts as a pci target (slave mode). when accessing host memory for descriptor or packet data transfer, th e rtl8110sc(l) acts as a pci bus master. all of the required pins and functions are implemente d in the rtl8110sc(l) as well as the optional pin, intab for support of interrupt requests. the bus interface supports 32-bit and 66mhz operation in addition to the more common 32-bit and 33mhz capabi lities. for more information, refer to the pci local bus specifications rev. 2.3, march 29, 2002. 6.1.1. byte ordering the rtl8110sc(l) can be configured to order the bytes of data on the pc i ad bus to conform to little-endian or big-endian orderi ng through the use of the endian b it of the c+ command register. when the rtl8110sc(l) is configured in big-endian mode, all the data in the data phase of either memory or i/o transaction to or from the rtl8110sc( l) is in big-endian mode. all data in the data phase of any pci configuration tr ansaction to rtl8110sc(l) should be little-endian, no matter whether the rtl8110sc(l) is set to big- endian or little-endian mode. when configured for little-endian (endian bit=0), the byte orientation for receive and transmit data and descriptors in system memory is as follows: 31 ~ 24 23 ~ 16 15 ~ 8 7 ~ 0 byte 3 byte 2 byte 1 byte 0 c/be[3] (msb) c/be[2] c/be[1] c/be[0] (lsb) figure 2. little-endian byte ordering when configured for big-endian mode (endian bit=1), the byte orienta tion for receive and transmit data and descriptors in system memory is as follows: 31 ~ 24 23 ~ 16 15 ~ 8 7 ~ 0 byte 0 byte 1 byte 2 byte 3 c/be[3] (lsb) c/be[2] c/be[1] c/be[0] (msb) figure 3. big-endian byte ordering 6.1.2. interrupt control interrupts are performed by asynchronously asserting the intab pin. this pin is an open drain output. the source of the interrupt can be de termined by reading the interrupt st atus register (isr). one or more bits in the isr will be set, denoting all currently pending interrupts. writing 1 to any bit in the isr register clears that bit. masking of specific interrupts can be accomp lished by using the interrupt mask www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 10 track id: jatr-1076-21 rev. 1.3 register (imr). assertion of intab can be prevented by clearing the inte rrupt enable bit in the interrupt mask register. this allows the system to defer interrupt processing as needed. 6.1.3. latency timer the pci latency timer described in ltr defines the ma ximum number of bus clocks that the device will hold the bus. once the device gains c ontrol of the bus and issues frameb, the latency timer will begin counting down. the ltr register speci fies, in units of pci bus clocks, the value of the latency timer of the rtl8110sc(l). when the rtl8110sc(l) asserts fr ameb, it enables its latency timer to count. if the rtl8110sc(l) deasserts frameb prior to count expiration, the content of the latency timer is ignored. otherwise, after the count expires, the rtl8110sc(l) ini tiates transaction termination as soon as its gntb is deasserted. software is able to re ad or write to ltr, and the default value is 00h. 6.1.4. 64-bit addressing the rtl8110sc(l) supports 64-bit addressing (dual address cycle) as a bus master for transferring descriptor and packet data information. dual addr ess cycle (dac) mode can be enabled or disabled through software. the rtl8110sc(l) only s upports 32-bit addre ssing as a target. 6.2. pci bus operation 6.2.1. target read a target read operation starts with the system ge nerating frameb, address, and either an io read (0010b) or memory read (0110b) command. if the 32-bi t address on the addre ss bus matches the io address range specified in ioar (f or i/o reads) or the memory addr ess range specified in mem (for memory reads), the rtl8110sc(l) will generate de vselb 2 clock cycles la ter (medium speed). the system must tri-state the address bus, and convert the c/be bus to byt e enables after th e address cycle. on the 2nd cycle after the assertion of devselb, a ll 32-bits of data and trdyb will become valid. if irdyb is asserted at that time, trdyb will be fo rced high on the next clock for 1 cycle, and then tri-stated. if frameb is asserted beyond the assertion of irdyb, the rtl8110sc(l) will still make data available as described above, but will also issue a disconnect . that is, it will assert the stopb signal with trdyb. stopb will remain asserted until frameb is detected as deasserted. figure 4. target read operation www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 11 track id: jatr-1076-21 rev. 1.3 6.2.2. target write a target write operation starts w ith the system generating frameb , address, and command (0011b or 0111b). if the upper 24 bits on the address bus match ioar (for i/o reads) or mem (for memory reads), the rtl8110sc(l) will generate devselb 2 clock cycl es later. on the 2nd cycl e after the assertion of devselb, the device will monitor the irdyb signa l. if irdyb is asserted at that time, the rtl8110sc(l) will assert trdyb. on the next cloc k the 32-bit double word w ill be latched in, and trdyb will be forced high for 1 cycle and then tr i-stated. target write ope rations must be 32-bits wide. if frameb is asserted beyond the assertion of irdyb, the rtl8110sc( l) will still latch the first double word as described above, but will also issue a disconnect. that is, it will assert the stopb signal with trdyb. stopb will remain asserted un til frameb is detected as deasserted. figure 5. target write operation www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 12 track id: jatr-1076-21 rev. 1.3 6.2.3. master read a master read operation starts with the rtl8110sc( l) asserting reqb. if gnt b is asserted within 2 clock cycles, frameb, address, and command will be generated 2 clocks after reqb (address and frameb for 1 cycle only). if gntb is asserted 3 cycles or later, frameb , address, and command will be generated on the clock following gntb. the device will wait for 8 cycles for the assertion of devselb. if devselb is not asserted within 8 clocks, the device will issue a master abort by a sserting frameb high for 1 cycle, and irdyb will be forced high on the following cycle. both signals will become tri-state on the cycle following their deassertion. on the clock edge after the generation of address and command, the address bus will become tri-state, and the c/be bus will contain valid byte enables. on the clock edge after frameb was asserted, irdyb will be asserted (and frameb will be deasserted if this is to be a single read operation). on the clock where both trdyb and devselb are detected as asserted, data will be latched in (and the byte enables will change if necessary). this will continue until the cycle following the deassertion of frameb. on the clock where the second to last read cycl e occurs, frameb will be forced high (it will be tri-stated 1 cycle later). on the next clock edge that the device detects tr dyb asserted, it will force irdyb high. it too will be tri- stated 1 cycle later. this will conclude the read operation. the rtl8110sc(l) will never force a wa it state during a read operation. figure 6. master read operation www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 13 track id: jatr-1076-21 rev. 1.3 6.2.4. master write a master write operation starts w ith the rtl8110sc(l) asserting reqb . if gntb is asserted within 2 clock cycles, frameb, address, and command will be generated 2 clocks after reqb (address and frameb for 1 cycle only). if gntb is asserted 3 cycles or later, frameb , address, and command will be generated on the clock following gntb. the device will wait 8 cycles for the assertion of devselb. if devselb is not asserted within 8 clocks, the device will issue a master abort by a sserting frameb high for 1 cycle. irdyb will be forced high on the following cycle. both signals wi ll become tri-state on the cycle following their deassertion. on the clock edge after the genera tion of address and command, the data bus will become valid, and the c/be bus will contain valid byte enables. on the cl ock edge after frameb was asserted, irdyb will be asserted (and frameb will be deasserted if this is to be a single read operation). on the clock where both trdyb and devselb are detected as asserted, va lid data for the next cycle will become available (and the byte enables will change if necessary). this will continue until the cycle following the deassertion of frameb. on the clock where the second to last write cycl e occurs, frameb will be forced high (it will be tri-stated 1 cycle later). on the next clock edge that the device detects tr dyb asserted, it will force irdyb high. it too will be tri-stated 1 cycle la ter. this will conclude the write operation. the rtl8110sc(l) will never force a wa it state during a write operation. figure 7. master write operation 6.2.5. configuration access configuration register accesses are similar to target reads and writes in that they are single data word transfers and are initiated by the system. for the system to initiate a configuration access, it must also generate idsel as well as the correct comma nd (1010b or 1011b) during the address phase. the rtl8110sc(l) will respond as it does during target ope rations. configuration reads must be 32-bits wide, but writes may access individual bytes. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 14 track id: jatr-1076-21 rev. 1.3 6.3. led functions the rtl8110sc(l) supports 4 led signals in 4 diffe rent configurable operation modes. the following sections describe the different led actions. 6.3.1. link monitor the link monitor senses the link integrity or if a station is down, such as link10, link100, link1000, link10/100/1000, link10/act, link 100/act, or link1000/act. wh enever link status is established, the specific link led pin is driven lo w. once a cable is disconn ected, the link led pin is driven high, indicating that no network connection exists. 6.3.2. rx led in 10/100/1000mbps mode, blinking of the rx led indicates that receive activity is occurring. power on receiving packet? led = high led = high for (100 +- 10) ms led = low for (12 +- 2) ms no yes figure 8. rx led www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 15 track id: jatr-1076-21 rev. 1.3 6.3.3. tx led in 10/100/1000mbps mode, blinking of the tx led indicates that transmit activity is occurring. power on transmitting packet? led = high led = high for (100 +- 10) ms led = low for (12 +- 2) ms no yes figure 9. tx led www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 16 track id: jatr-1076-21 rev. 1.3 6.3.4. tx/rx led in 10/100/1000mbps mode, blinking of the tx/rx led i ndicates that both transm it and receive activity is occurring. power on tx/rx packet? led = high led = high for (100 +- 10) ms led = low for (12 +- 2) ms no yes figure 10. tx/rx led www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 17 track id: jatr-1076-21 rev. 1.3 6.3.5. link/act led in 10/100/1000mbps mode, blinking of the link/act led indicates that the rtl8110sc(l) is linked and operating properly. when this led is high for extended periods, it indicates that a link problem exists. power on link? led = high led = low led = low for (12 +- 2) ms no yes tx/rx packet? yes no led = high for (100 +- 10) ms figure 11. link/act led www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 18 track id: jatr-1076-21 rev. 1.3 6.4. phy transceiver 6.4.1. phy transmitter in 10mbps mode, the tx mac retrieve s packet data from the tx buffe r manager and sends it out through the transmitting physical layer in terface. the transmit 4-bit nibbles (txd[3:0]) clocked at 2.5mhz (txc), are serialized into 10mbps serial data. th en, the 10mbps serial data is converted into a manchester-encoded data stream and is transm itted onto the media by the dac converter. in 100mbps mode, the transmitted 4-bit nibbles (txd[ 3:0]) from the mac, clocked at 25mhz (txc), are converted into 5b symbol code via 4b/5b coding technology, sc rambling, and serializing before being converted to 125mhz nrz and nrzi signals. af ter that, the nrzi signal is passed to the mlt-3 encoder, then to the dac converter for transmission onto the media. in 1000mbps mode, the rtl8110sc(l)?s pcs layer re ceives data bytes from the mac through the gmii interface and performs the generation of continuous code-groups through 4d-pam5 coding technology. then those code groups are passed thr ough a waveform shaping filter to minimize emi effects, and are transmitted onto the 4-pa ir cat5 cable at 125mbaud/s through a dac. 6.4.2. phy receiver in mii (10mbps) mode, the received differential si gnal is converted into a manchester-encoded data stream. the stream is processed with a manchester de coder, and is de-serialized into 4-bit wide nibbles. the 4-bit nibbles are presented to the mii interf ace at a clock speed of 2.5mhz. in 100mbps mode, the mlt-3 signal is processed with an adc, equalizer, blw (baseline wander) correction, timing recovery, mlt-3 and nrzi decoder, descrambler, 4b/5b decoder, and then is presented to the mii interface in 4-bit wide nibbles at a clock speed of 25mhz. in gmii mode, the input signal from the media fi rst passes through the on-ch ip sophisticated hybrid circuit to subtract the transmitted signal from the i nput signal for effective reduction of near-end echo. afterwards, the received signal is processed with adaptive equalization, blw (baseline wander) correction, cross-talk cancellati on, echo cancellation, timing recover y, error correction, and 4d-pam5 decoding. then the 8-bit wide data is recovered and is sent to the gm ii interface at a clock speed of 125mhz. the rx mac retrieves the packet data from the receive mii/gmii interf ace and sends it to the rx buffer manager. 6.5. next page if 1000base-t mode is advertised, three additional next pages are automatica lly exchanged between the two link partners. users can set phy reg4.15 to 1 to manually exchange extra next pages via reg7 and reg8 as defined in ieee 802.3ab. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 19 track id: jatr-1076-21 rev. 1.3 6.6. eeprom interface the rtl8110sc(l) requires the attachment of an external eeprom. the 93c46 is a 1k-bit eeprom (the 93c56 is a 2k-bit eeprom, the 93c66 is a 4k -bit eeprom). the eeprom interface provides the ability for the rtl8110sc(l) to read from and write data to an external serial eeprom device. values in the external eeprom allow default fields in pci configuration space and i/o space to be overridden following a power-on or software ee prom auto-load command. the rtl8110sc(l) will auto-load values from the eeprom. if the eeprom is not present, the r tl8110sc(l) initialization uses default values for the appropriate configurati on and operational registers. software can read and write to the eeprom using bit-bang accesses via the 9346cr register, or using pci vpd. the interface consists of eesk, eecs, eedo, and eedi. table 10. eeprom interface eeprom description eecs 93c46 (93c56/93c66) chip select. eesk eeprom serial data clock. eedi/aux input data bus/input pin to detect if aux. power exists or not on initial power-on. this pin should be connected to boot prom. to support wakeup from acpi d3cold or apm power-down, this pin must be pulled high to aux. power via a resistor. if this pin is not pulled high to aux. power, the rtl8110sc(l) assumes that no aux. power exists. eedo output data bus. 6.7. power management the rtl8110sc(l) is compliant with acpi (rev 1.0, 1.0b, 2.0), pci power management (rev 1.1), and network device class power management referen ce specification (v1.0a), such as to support an operating system-directed power management (ospm) environment. the rtl8110sc(l) can monitor the network for a wa keup frame, a magic packet, or a re-linkok, and notify the system via pme# when such a packet or event occurs. then, the whole system can be restored to a normal state to process incoming jobs. when the rtl8110sc(l) is in power down mode (d1 ~ d3): ? the rx state machine is stopped, and the rtl8110s c(l) monitors the network for wakeup events such as a magic packet, wakeup frame, and/or re-l inkok, in order to wake up the system. when in power down mode, the rtl8110sc(l) will not reflect the status of any incoming packets in the isr register and will not receive any p ackets into the rx fifo buffer. ? the fifo status and packets that have already been received into the rx fifo before entering power down mode are held by the rtl8110sc(l). ? transmission is stopped. pci bus master mode is stopped. the tx fifo buffer is held. ? after restoration to a d0 state, the rtl8110sc(l) transfers data that was not moved into the tx fifo buffer during power down mode. packets that we re not transmitted completely last time are re-transmitted. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 20 track id: jatr-1076-21 rev. 1.3 the d3cold_support_pme bit (bit15, pmc register) a nd the aux_i_b2:0 bits (bit8 :6, pmc register) in pci configuration space depend on the exis tence of aux power (bit15, pmc) = 1. if eeprom d3cold_support_pme bit (bit15, pmc) = 0, the above 4 bi ts are all 0?s. example: if eeprom d3c_support_pme = 1: ? if aux. power exists, then pmc in pci c onfig space is the same as eeprom pmc (if eeprom pmc = c2 f7, then pci pmc = c2 f7) ? if aux. power is absent, then pmc in pci conf ig space is the same as eeprom pmc except the above 4 bits are all 0?s (if eeprom pmc = c2 f7, then pci pmc = 02 76) in the above case, if wakeup support is desired when main power is off, it is suggested that the eeprom pmc be set to c2 f7 (realtek eeprom default value). if eeprom d3c_support_pme = 0: ? if aux. power exists, then pmc in pci c onfig space is the same as eeprom pmc (if eeprom pmc = c2 77, then pci pmc = c2 77) ? if aux. power is absent, then pmc in pci conf ig space is the same as eeprom pmc except the above 4 bits are all 0?s (if eeprom pmc = c2 77, then pci pmc = 02 76) in the above case, if wakeup support is not desired wh en main power is off, it is suggested that the eeprom pmc be set to 02 76. link wakeup occurs only when the following conditions are met: ? the linkup bit (config3#4) is set to 1, the pmen bit (config1#0) is set to 1, and the pme# can be asserted in the current power state. magic packet wakeup occurs only when the following conditions are met: ? the destination address of the received magic packet is accepta ble to the rtl8110sc(l), e.g. a broadcast, multicast, or unicast packet addressed to the current rtl8110sc(l) adapter. ? the received magic packet does not contain a crc error. ? the magic bit (config3#5) is set to 1, the pmen b it (config1#0) is set to 1, and the pme# can be asserted in the current power state. ? the magic packet pattern matches, i.e. 6 * ffh + misc (can be none) + 16 * did (destination id) in any part of a valid (f ast) ethernet packet. a wakeup frame event occurs only wh en the following conditions are met: ? the destination address of the received wakeup frame is acceptable to the rtl8110sc(l), e.g. a broadcast, multicast, or unicast address to the current rtl8110sc(l) adapter. ? the received wakeup frame does not contain a crc error. ? the pmen bit (config1#0) is set to 1. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 21 track id: jatr-1076-21 rev. 1.3 ? the 16-bit crc* of the received wakeup frame matches the 16-bit crc* of the sample wakeup frame pattern given by the local machine?s os. or, th e rtl8110sc(l) is configured to allow direct packet wakeup, e.g. a broadcast, multic ast, or unicast network packet. *16-bit crc: the rtl8110sc(l) supports two normal wakeup frames (covering 64 mask bytes from offset 0 to 63 of any incoming network packet) and three long wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet). the pme# signal is asserted only wh en the following conditions are met: ? the pmen bit (bit0, config1) is set to 1. ? the pme_en bit (bit8, pmcsr) in pc i configuration space is set to 1. ? the rtl8110sc(l) may assert pme# in the current power state or in isolation state, depending on the pme_support (bit15-11) setting of the pmc register in pci configuration space. ? a magic packet, linkup, or wakeup frame has been received. ? writing a 1 to the pme_status (bit15) of the pmcsr register in the pci configuration space clears this bit and causes the rtl8110sc(l) to stop asserting a pme# (if enabled). when the device is in power down mode, e.g. d1-d3, the io and mem spaces are all disabled. after a rst# assertion, the device?s power stat e is restored to d0 automatically if the original power state was d3 cold . there is no hardware delay at th e device?s power state transition. when in acpi mode, the device does not support pme (power management enable) from d0 (this is the realtek default setting of the pmc register auto-loaded from eeprom). the sett ing may be changed from the eeprom, if required. the rtl8110sc(l) also supports the legacy l an wake-up function. the lw ake pin is used to notify legacy motherboards to execute the wake-up pro cess whenever the device receives a wakeup event, such as a magic packet. the lwake signal is asserted acco rding to the following settings: 1. lwpme bit (bit4, config4): ? lwake can only be asserted when pmeb is asserted and isolateb is low. ? lwake is asserted whenever a wakeup event occurs. 2. bit1 of delay byte (offset 1fh, eeprom): ? lwake signal is enabled. ? lwake signal is disabled. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 22 track id: jatr-1076-21 rev. 1.3 7. characteristics 7.1. absolute maximum ratings warning: absolute maximum ratings are limits beyond which permanent damage may be caused to the device, or device reliability will be affected. all voltages are specified reference to gnd unless otherwise specified. table 11. absolute maximum ratings description/symbol minimum maximum unit supply voltage (vdd33, avdd33) -0.5 4 v supply voltage (avdd18) -0.5 2 v supply voltage (vdd15, avdd15) -0.5 1.8 v input voltage (dcinput) -0.5 vdd33 + 0.5 v output voltage (dcoutput) -0.5 vdd33 + 0.5 v storage temperature -55 +125 c 7.2. recommended operating conditions table 12. recommended operating conditions description pins minimum typical maximum unit vdd33, avdd33 3.0 3.3 3.6 v avdd18 1.6 1.8 2.0 v supply voltage vdd vdd15, avdd15 1.35 1.5 1.65 v ambient temperature t a 0 - 70 c maximum junction temperature - - 125 c 7.3. crystal requirements table 13. crystal requirements symbol description/condition minimum typical maximum unit f ref parallel resonant crystal reference frequency, fundamental mode, at-cut type. - 25 - mhz f ref stability parallel resonant crystal frequency stability, fundamental mode, at-cut type. t a =25 c. -50 - +50 ppm f ref tolerance parallel resonant crystal frequency tolerance, fundamental mode, at-cut type. t a =-20 c ~+70 c. -30 - +30 ppm f ref duty cycle reference clock input duty cycle. 40 - 60 % c l load capacitance. - - 27 pf esr equivalent series resistance. - - 10 ? dl drive level. - - 0.5 mw www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 23 track id: jatr-1076-21 rev. 1.3 7.4. thermal characteristics table 14. thermal characteristics parameter minimum maximum units storage temperature -55 +125 c operating temperature 0 70 c 7.5. dc characteristics table 15. dc characteristics symbol parameter conditions minimum typical maximum units vdd33 3.3v supply voltage - 3.0 3.3 3.6 v avdd18 1.8v supply voltage - 1.6 1.8 2.0 v vdd15, avdd15 1.5v supply voltage - 1.35 1.5 1.65 v v oh minimum high level output voltage i oh = -8ma 0.9 * vdd33 - vdd33 v v ol maximum low level output voltage i ol = 8ma - - 0.1 * vdd33 v v ih minimum high level input voltage - 0.5 * vdd33 - vdd33+0.5 v v il maximum low level input voltage - -0.5 - 0.3 * vdd33 v i in input current v in = vdd33 or gnd -1.0 - 1.0 ua i oz tri-state output leakage current v out = vdd33 or gnd -10 - 10 ua icc33 average operating supply current from 3.3v - - tbd - ma icc15 average operating supply current from 1.2v - - tbd - ma www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 24 track id: jatr-1076-21 rev. 1.3 7.6. ac characteristics 7.6.1. serial eeprom interface timing 93c46(64*16)/93c56(128*16)/93c66(256*16) eesk eecs eedi eedo 1 1 0 an a2 a0 a1 dn d1 d0 eesk (read) (write) (read) (write) 0 tcs eesk eecs eedi eedo 11 0ana0 ... dn tcs ... d0 busy ready high impedance high impedance twp eecs eedi eedo eedo (read) (program) status valid tsk tskh tskl tcss tdis tdih tdos tdoh tcsh tsv figure 12. serial eeprom interface timing table 16. eeprom access timing parameters symbol parameter eeprom type min. max. unit tcs minimum cs low time 9346/9356 1000/250 - ns twp write cycle time 9346/9356 - 10/10 ms tsk sk clock cycle time 9346/9356 4/1 - s tskh sk high time 9346/9356 1000/500 - ns tskl sk low time 9346/9356 1000/250 - ns tcss cs setup time 9346/9356 200/50 - ns tcsh cs hold time 9346/9356 0/0 - ns tdis di setup time 9346/9356 400/50 - ns tdih di hold time 9346/9356 400/100 - ns tdos do setup time 9346/9356 2000/500 - ns tdoh do hold time 9346/9356 - 2000/500 ns tsv cs to status valid 9346/9356 - 1000/500 ns www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 25 track id: jatr-1076-21 rev. 1.3 7.7. pci bus operation timing 7.7.1. pci bus timing parameters table 17. pci bus timing parameters 66mhz 33mhz symbol parameter min max min symbol parameter t val clk to signal valid delay-bused signals 2 6 2 11 ns t val(ptp) clk to signal valid delay-point to point 2 6 2 12 ns t on float to active delay 2 - 2 - ns t off active to float delay - 14 28 ns t su input setup time to clk-bused signals 3 - 7 - ns t su(ptp) input setup time to clk-point to point 5 - 10 - ns t h input hold time from clk 0 - 0 - ns t rst reset active time after power stable 1 - 1 - ms t rst-clk reset active time after clk stable 100 - 100 - s t rst-off reset active to output float delay - 40 40 ns t rhfa rstb high to first configuration access 2^25 - 2^25 - clocks t rhff rstb high to first frameb assertion 5 - 5 - clocks clk output delay tri-state output v_th v_tl v_test v_trise, v_tfall t_off t_val t_on v_test v_test figure 13. output timing measurement conditions www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 26 track id: jatr-1076-21 rev. 1.3 clk input v_th v_tl v_test v_test t_su v_th v_tl t_h v_test inputs valid v_max figure 14. input timing measurement conditions table 18. measurement condition parameters symbol level units vth 0.6vcc v vtf 0.2vcc v vtest 0.4vcc v vtrise 0.285vcc v vtfall 0.615vcc v vmax 0.4vcc v input signal edge rate 1 v/ns 7.7.2. pci clock specification 0.6vcc 0.2vcc 0.4vcc, peak-to-peak (minimum) 0.3vcc t_high t_low t_cyc 0.5vcc 0.4vcc figure 15. 3.3v clock waveform www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 27 track id: jatr-1076-21 rev. 1.3 clk (@ device #1) clk (@ device #2) t_skew t_skew t_skew v_ih v_ih v_il v_il v_test v_test figure 16. clock skew diagram table 19. clock and reset specifications 66mhz 33mhz symbol parameter min max min symbol parameter tcyc clk cycle time 15 30 30 ns thigh clk high time 6 11 ns tlow clk low time 6 11 ns -- clk slew rate 1.5 4 1 4 v/ns -- rst# slew rate 50 - 50 - mv/ns tskew clk skew 1 2 ns 7.7.3. pci transactions devselb c/be3-0b irdyb trdyb ad31-0 address clk 1 23456789 frameb 10 data bus cmd be3-0b figure 17. i/o read www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 28 track id: jatr-1076-21 rev. 1.3 devselb c/be3-0b irdyb trdyb ad31-0 address clk 1 23456789 frameb 10 data bus cmd be3-0b figure 18. i/o write devselb c/be3-0b irdyb trdyb ad31-0 address clk 1 23456789 frameb 10 data bus cmd be3-0b idsel figure 19. configuration read www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 29 track id: jatr-1076-21 rev. 1.3 devselb c/be3-0b irdyb trdyb ad31-0 address clk 1 23456789 frameb 10 data bus cmd be3-0b idsel figure 20. configuration write address data address data ad gntb-a gntb-b frameb reqb-b clk 1 23456789 reqb-a 10 figure 21. bus arbitration www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 30 track id: jatr-1076-21 rev. 1.3 devselb irdyb trdyb wait data transfer wait wait data transfer data transfer ad31-0 address data-1 data-2 data-3 clk 1 23456789 frameb c/be3-0b bus cmd be3-0b figure 22. memory read below 4gb devselb c/be3-0b irdyb trdyb ad31-0 address data-1 data-2 data-3 bus cmd be3-0b-1 be3-0b-2 clk 1 23456789 frameb wait data transfer wait wait data transfer data transfer be3-0b-3 figure 23. memory write below 4gb www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 31 track id: jatr-1076-21 rev. 1.3 devselb irdyb trdyb clk 1 23456789 frameb stopb figure 24. target initiated termination - disconnect devselb irdyb trdyb clk 1 23456789 frameb stopb figure 25. target initiated termination - abort www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 32 track id: jatr-1076-21 rev. 1.3 devselb irdyb trdyb clk 1 23456789 frameb fast sub slow med no response acknowledge figure 26. master initiated termination - abort bus cmd address data address data perr# clk 1 23456789 frameb 10 par/par64 ad c/be# serr# be# bus cmd be# figure 27. parity operation ? one example www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 33 track id: jatr-1076-21 rev. 1.3 devselb c/be3-0b irdyb trdyb ad31-0 lo-addr clk 1 23456789 frameb wait data transfer wait wait data transfer data transfer 10 bus cmd be3-0b data-1 data-2 data-3 hi-addr dac cmd figure 28. memory read above 4gb (dac) devselb c/be3-0b irdyb trdyb ad31-0 lo-addr data-1 data-2 data-3 bus cmd be3-0b-1 be3-0b-2 clk 1 23456789 frameb wait data transfer wait wait data transfer data transfer be3-0b-3 10 hi-addr dac cmd figure 29. memory write above 4gb (dac) www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 34 track id: jatr-1076-21 rev. 1.3 8. mechanical dimensions 8.1. 128-pin qfp mechanical dimensions see the mechanical dimensions notes on the next page. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 35 track id: jatr-1076-21 rev. 1.3 8.2. notes for 128-pin qfp dimensions symbol dimensions in inches dimensions in mm notes : min typical max min typical max 1. dimensions d & e do not include interlead flash. a - - 0.134 - - 3.40 2. dimension b does not include dambar protrusion/intrusion. a1 0.004 0.010 0.036 0.10 0.25 0.91 3. controlling dimension: millimeter a2 0.102 0.112 0.122 2.60 2.85 3.10 4. general appearance spec. should be based on final visual inspection. b 0.005 0.009 0.013 0.12 0.22 0.32 c 0.002 0.006 0.010 0.05 0.15 0.25 d 0.541 0.551 0.561 13.75 14.00 14.25 title: 128 qfp (14x20 mm) package outline e 0.778 0.787 0.797 19.75 20.00 20.25 -cu l/f, footprint 3.2 mm e 0.020 bsc 0.50 bsc leadframe material h d 0.665 0.677 0.689 16.90 17.20 17.50 approve doc. no. h e 0.902 0.913 0.925 22.90 23.20 23.50 version l 0.027 0.035 0.043 0.68 0.88 1.08 page l 1 0.053 0.063 0.073 1.35 1.60 1.85 check dwg no. q128 - 1 y - - 0.004 - - 0.10 date 0 - 12 0 - 12 realtek semiconductor corp. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 36 track id: jatr-1076-21 rev. 1.3 8.3. 128-pin lqfp mechanical dimensions see the mechanical dimensions notes on the next page. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 37 track id: jatr-1076-21 rev. 1.3 8.4. notes for 128-pin lqfp dimensions symbol dimension in inch dimension in mm min nom max min nom max a - - 0.063 - - 1.60 a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.053 0.055 0.057 1.35 1.40 1.45 b 0.007 0.009 0.011 0.17 0.22 0.27 b 1 0.007 0.008 0.009 0.17 0.20 0.23 c 0.004 - 0.008 0.09 - 0.20 c 1 0.004 - 0.006 0.09 - 0.16 d 0.862 0.866 0.870 21.90 22.00 22.10 d 1 0.783 0.787 0.791 19.90 20.00 20.10 e 0.626 0.630 0.634 15.90 16.00 16.10 e 1 0.547 0.551 0.555 13.90 14.00 14.10 e 0.020 bsc 0.50 bsc l 0.018 0.024 0.030 0.45 0.60 0.75 l 1 0.039 ref 1.00 ref r 1 0.003 - - 0.08 - - r 2 0.003 - 0.008 0.08 - 0.20 s 0.008 - - 0.20 - - 0 3.5 7 0 3.5 7 1 4 typ 4 typ 2 12 typ 12 typ 3 12 typ 12 typ notes: 1.to be determined at seating plane -c- 2.dimensions d 1 and e 1 do not include mold protrusion. d 1 and e 1 are maximum plastic body size dimensions including mold mismatch. 3.dimension b does not include dambar protrusion. dambar cannot be located on the lower radius of the foot. 4.exact shape of each corner is optional. 5.these dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 6. a 1 is defined as the distance from the seating plane to the lowest point of the package body. 7.controlling dimension: millimeter. 8. reference document: jedec ms-026, bhb title: 128ld lqfp (14x20x1.4mm) package outline cu l/f, footprint 2.0 mm leadframe material: c7025 1/1h approve doc. no. version page 1 of 1 check dwg no. dc128-sw1 date 26 nov. 2002 realtek semiconductor corp. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8110sc(l) datasheet integrated gigabit ethernet controller (lom) (minipci) 38 track id: jatr-1076-21 rev. 1.3 9. ordering information table 20. ordering information part number package status RTL8110SC-GR 128-pin qfp green package rtl8110scl-gr 128-pin lqfp green package note: see page 3 for package identification information. realtek semiconductor corp. headquarters no. 2, innovation road ii hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com.tw www.datasheet.co.kr datasheet pdf - http://www..net/

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